首页> 外国专利> Multilayer high quality gate dielectric for low-temperature polysilicon TFT

Multilayer high quality gate dielectric for low-temperature polysilicon TFT

机译:用于低温多晶硅TFT的多层高质量栅极电介质

摘要

Method and apparatus useful is disclosed for forming a high quality gate dielectric layer in MOS TFT devices using a high density plasma oxide and (HDPO) process. In one embodiment, constitutes a dielectric interface HDPO process layer is formed on the drain region on the channel, source, and, then, a high-quality gate deposited on the HDPO layer on one or more dielectric layers I to form a dielectric layer. HDPO process growing an interfacial layer by injecting a gas containing an oxidizing source, and also controls a plasma in general, to generate a plasma using a capacitively coupled RF transmitting device and / or induction occurred on the substrate makes. Next, I deposited on the substrate by using the PECVD deposition process CVD or the second dielectric layer. Furthermore, aspects of the present invention provides a cluster tool for accommodating the special plasma processing chamber at least one can deposit a high quality gate dielectric layer.
机译:公开了用于使用高密度等离子体氧化物和(HDPO)工艺在MOS TFT器件中形成高质量栅极介电层的方法和设备。在一个实施例中,构成介电界面的HDPO工艺层形成在沟道,源极上的漏极区域上,然后,在一个或多个介电层I上的HDPO层上沉积高质量栅极,以形成介电层。 HDPO通过注入包含氧化源的气体来生长界面层,并且通常还控制等离子体,以使用电容耦合RF发射设备和/或在基板上产生感应来产生等离子体。接下来,我通过使用PECVD沉积工艺CVD或第二介电层沉积在衬底上。此外,本发明的各方面提供了一种用于容纳特殊等离子体处理室的群集工具,其中至少一个可以沉积高质量的栅极介电层。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号