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Multilayer high quality gate dielectric for low-temperature polysilicon TFT
Multilayer high quality gate dielectric for low-temperature polysilicon TFT
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机译:用于低温多晶硅TFT的多层高质量栅极电介质
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摘要
Method and apparatus useful is disclosed for forming a high quality gate dielectric layer in MOS TFT devices using a high density plasma oxide and (HDPO) process. In one embodiment, constitutes a dielectric interface HDPO process layer is formed on the drain region on the channel, source, and, then, a high-quality gate deposited on the HDPO layer on one or more dielectric layers I to form a dielectric layer. HDPO process growing an interfacial layer by injecting a gas containing an oxidizing source, and also controls a plasma in general, to generate a plasma using a capacitively coupled RF transmitting device and / or induction occurred on the substrate makes. Next, I deposited on the substrate by using the PECVD deposition process CVD or the second dielectric layer. Furthermore, aspects of the present invention provides a cluster tool for accommodating the special plasma processing chamber at least one can deposit a high quality gate dielectric layer.
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