Test method for an integrated circuit having a plurality of clock domains

摘要

The integrated circuit comprises multiple clock domains and (10, 12). Through (100,14,104) scan chain, test data is input to the integrated circuit. In the test mode, the connection between the functional input second clock domain (12) and the function output terminal first clock domain (10) is interrupted. Test data is supplied to the input terminal function from (100,14,104) scan chain, the test response is taken from the function output. When the test result is captured scan in (21), in order to ensure that the timing clock drift between regions does not affect the test, by using a delay circuit (24, 28), scan (21 I delaying the transfer of test results to the function from the input end). Then, the test result is output through the scan chain.