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Production mannered null multiple deep p forma well

机译:生产方式为零倍的深深预估井

摘要

PROBLEM TO BE SOLVED: To provide a fit-in type flash memory cell structure which performs writing and deleting via a channel, and a method of manufacturing the same. SOLUTION: A CMOS device and a flash memory cell are combined, and a flash memory structure and the CMOS device are fabricated on a base at the same time to reduce manufacturing costs and processes. Furthermore, the CMOS device reserves functions for both high- and low-voltage operations to effectively improve the operation efficiency between the flash memory cell and the CMOS device. Thus a total deposit thereof is smaller than when they are separately fabricated before being combined.
机译:解决的问题:提供一种装配型闪存单元结构及其制造方法,该结构通过通道执行写入和删除。解决方案:将CMOS器件和闪存单元组合在一起,并同时在基座上制造闪存结构和CMOS器件,以降低制造成本和工艺。此外,CMOS器件保留用于高电压和低压操作的功能,以有效地提高闪存单元和CMOS器件之间的操作效率。因此,它们的总沉积小于它们在组合之前分开制造的沉积。

著录项

  • 公开/公告号JP4022049B2

    专利类型

  • 公开/公告日2007-12-12

    原文格式PDF

  • 申请/专利权人 力晶半導體股▲ふん▼有限公司;

    申请/专利号JP20010150986

  • 发明设计人 楊 清松;徐 清祥;

    申请日2001-05-21

  • 分类号H01L21/8247;H01L27/115;H01L29/788;H01L29/792;H01L21/8238;H01L27/092;H01L21/8234;H01L27/088;H01L27/10;

  • 国家 JP

  • 入库时间 2022-08-21 20:17:48

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