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HIERARCHICAL ANALOG LAYOUT SYNTHESIS AND OPTIMIZATION FOR INTEGRATED CIRCUITS
HIERARCHICAL ANALOG LAYOUT SYNTHESIS AND OPTIMIZATION FOR INTEGRATED CIRCUITS
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机译:集成电路的层次模拟布局综合与优化
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摘要
In embodiment of the invention, a method of synthesizing a layout of an integrated circuit chip including analog circuitry is disclosed. The method includes receiving a circuit netlist of an integrated circuit chip including analog circuitry; representing and manipulating a hierarchical analog circuit layout including device placement and net routing in response to the circuit netlist, the hierarchical analog circuit layout including a plurality of levels of layout hierarchy; and passing layout information from one level of the layout hierarchy to an adjacent level of the layout hierarchy to synthesize the layout of the integrated circuit chip.
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