首页>
外国专利>
Bottom Dielectric Structures and High-K Memory Structures in Memory Devices and Methods for Expanding a Second Bit Operation Window
Bottom Dielectric Structures and High-K Memory Structures in Memory Devices and Methods for Expanding a Second Bit Operation Window
展开▼
机译:存储器件中的底部电介质结构和高K存储器结构以及扩展第二位操作窗口的方法
展开▼
页面导航
摘要
著录项
相似文献
摘要
Methods and structures are described for increasing a memory operation window in a charge trapping memory having a plurality of memory cells in which each memory cell is capable of storing multiple bits per memory cell. In a first aspect of the invention, a first method to increase a memory operation window in a two-bit-per-cell memory is described by applying a positive gate voltage, +Vg, to erase a memory cell to a negative voltage level. Alternatively, a negative gate voltage, −Vg, is applied to the two-bit-per-cell memory for erasing the memory cell to a negative voltage level. A second method to increase a memory operation window is to erase a memory cell to a voltage level that is lower than an initial voltage threshold level. These two erasing methods can be implemented either before a programming step (i.e., a pre-program erase operation) or after a programming step (i.e., a post-program erase operation).
展开▼