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ARCHITECTURE FOR CONFIGURABLE BUS ARBITRATION IN MULTIBUS SYSTEMS WITH CUSTOMIZABLE MASTER AND SLAVE CIRCUITS
ARCHITECTURE FOR CONFIGURABLE BUS ARBITRATION IN MULTIBUS SYSTEMS WITH CUSTOMIZABLE MASTER AND SLAVE CIRCUITS
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机译:具有可自定义主从电路的多总线系统中可配置总线仲裁的体系结构
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摘要
An integrated multibus system includes a first and second master devices coupled to first and second master busses. A slave device is coupled to the first and second master busses through a first multiplexer, a first address decoder coupled to the first master bus having an output associated with the slave device, a second address decoder coupled to the second master bus and having an output associated with the slave device. A first arbiter circuit multiplexer has an output coupled to a select input of the first multiplexer. A first arbiter circuit is coupled to the outputs of the first and second address decoders, the first arbiter circuit having an output that is a predetermined function of the address decoder outputs and is coupled to an input of the first arbiter circuit multiplexer. A configurable logic area has a first net coupled to an input of the arbiter circuit multiplexer.
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