首页> 外国专利> MULTI-BIT HIGH-DENSITY MEMORY DEVICE AND ARCHITECTURE AND METHOD OF FABRICATING MULTI-BIT HIGH-DENSITY MEMORY DEVICES

MULTI-BIT HIGH-DENSITY MEMORY DEVICE AND ARCHITECTURE AND METHOD OF FABRICATING MULTI-BIT HIGH-DENSITY MEMORY DEVICES

机译:多位高密度存储器设备和体系结构以及制造多位高密度存储器设备的方法

摘要

A structure, memory devices using the structure, and methods of fabricating the structure. The structure includes: an array of nano-fins, each nano-fin comprising an elongated block of semiconductor material extending axially along a first direction, the nano-fins arranged in groups of at least two nano-fins each, wherein ends of nano-fins of each adjacent group of nano-fins are staggered with respect to each other on both a first and a second side of the array; wherein nano-fins of each group of nano-fins are electrically connected to a common contact that is specific to each group of nano-fins such that the common contacts comprise a first common contact on the first side of the array and a second common contact on the second side of the array; and wherein each group of nano-fins has at least two gates that electrically control the conductance of nano-fins of the each group of nano-fins.
机译:一种结构,使用该结构的存储器件以及制造该结构的方法。该结构包括:纳米鳍片的阵列,每个纳米鳍片包括沿第一方向轴向延伸的半导体材料的细长块,纳米鳍片以至少两个纳米鳍片的组布置,其中,纳米鳍片的末端每个相邻的纳米鳍片组的鳍片在阵列的第一和第二侧上彼此交错。其中每组纳米鳍的纳米鳍电连接到特定于每组纳米鳍的公共触点,使得该公共触点包括在阵列的第一侧上的第一公共触点和第二公共触点在阵列的第二侧;其中每组纳米鳍片具有至少两个栅极,所述至少两个栅极电控制每组纳米鳍片中的纳米鳍片的电导。

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