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Method for extracting and modeling semiconductor device series resistance and for simulating a semiconductor device with use thereof

机译:提取和建模半导体器件串联电阻并使用其模拟半导体器件的方法

摘要

Semiconductor device junction simulation is carried out utilizing models that are developed with series resistance extractions that improve their fidelity particularly in the high current regions of device operation. The models may also be tailored to account for geometric considerations of the semiconductor devices thereby allowing for a more flexible model and simulation by providing for geometric scaling capabilities.
机译:半导体器件的结仿真是利用通过串联电阻提取开发的模型来进行的,这些模型可以提高保真度,特别是在器件工作的高电流区域。还可以定制模型以考虑半导体器件的几何考虑,从而通过提供几何缩放能力而允许更灵活的模型和仿真。

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