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Method of measuring an effective channel length and an overlap length in a metal-oxide semiconductor field effect transistor

机译:在金属氧化物半导体场效应晶体管中测量有效沟道长度和重叠长度的方法

摘要

In a method of measuring an effective channel length and an overlap length, first to third metal-oxide semiconductor field effect transistors (MOSFETs) including first to third gate patterns, respectively, are formed on a substrate. A parasitic capacitance between the gate patterns and the substrate in the MOSFETs is determined based on first and second capacitances, which are measured by applying a first voltage between the gate patterns and the substrate. A second voltage is applied between the first gate pattern and the substrate in the first MOSFET and a third voltage between the third gate pattern and the substrate in the third MOSFET to measure capacitances. The capacitances are treated to obtain third and fourth capacitances excluding the parasitic capacitance. Overlap lengths of the gate patterns are obtained based on the third and fourth capacitances. Effective channel lengths of the gate patterns are obtained based on the overlap length.
机译:在测量有效沟道长度和重叠长度的方法中,分别包括第一至第三栅极图案的第一至第三金属氧化物半导体场效应晶体管(MOSFET)形成在基板上。基于第一电容和第二电容来确定MOSFET中栅极图案和衬底之间的寄生电容,这是通过在栅极图案和衬底之间施加第一电压来测量的。在第一栅极图案和第一MOSFET中的衬底之间施加第二电压,并且在第三栅极图案和第三MOSFET中的衬底之间施加第三电压以测量电容。处理电容以获得除寄生电容之外的第三电容和第四电容。基于第三和第四电容来获得栅极图案的重叠长度。基于重叠长度获得栅极图案的有效沟道长度。

著录项

  • 公开/公告号US7405090B2

    专利类型

  • 公开/公告日2008-07-29

    原文格式PDF

  • 申请/专利权人 YONG-UN JANG;

    申请/专利号US20060638001

  • 发明设计人 YONG-UN JANG;

    申请日2006-12-13

  • 分类号G01R31/26;H01L21/66;H01L21/336;

  • 国家 US

  • 入库时间 2022-08-21 20:10:22

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