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Fault list and test pattern generating apparatus and method, fault list generating and fault coverage calculating apparatus and method

机译:故障列表和测试模式生成装置和方法,故障列表生成和故障覆盖率计算装置和方法

摘要

The test pattern generating apparatus contains a module configured to generate short information indicative of a relationship between a logical value of an input signal of a cell and a voltage of an electrically shorted portion assumed at an output terminal of the cell; a module configured to calculate a logical threshold value of the input terminal of the cell so as to generate logical threshold value information; a module configured to extract a bridge fault information from layout information of an LSI; a module configured to generate a bridge fault list including a bridge fault type based on the bridge fault information, the short information, and the logical threshold value information; and a module configured to generate a test pattern which detects bridge faults in an adjacent signal wire pair and a bridge fault type.
机译:所述测试图案生成装置包括模块,该模块被配置为生成指示单元的输入信号的逻辑值与在单元的输出端子处假设的电短路部分的电压之间的关系的短信息;以及模块,被配置为计算单元的输入端子的逻辑阈值,以生成逻辑阈值信息;模块,被配置为从LSI的布局信息中提取桥故障信息;模块,被配置为基于桥故障信息,短路信息和逻辑阈值信息,生成包括桥故障类型的桥故障列表;所述模块被配置为生成测试模式,所述测试模式检测相邻信号线对中的桥故障和桥故障类型。

著录项

  • 公开/公告号US7392146B2

    专利类型

  • 公开/公告日2008-06-24

    原文格式PDF

  • 申请/专利权人 YASUYUKI NOZUYAMA;

    申请/专利号US20070622559

  • 发明设计人 YASUYUKI NOZUYAMA;

    申请日2007-01-12

  • 分类号G01R31/00;G01R31/14;

  • 国家 US

  • 入库时间 2022-08-21 20:10:20

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