Design techniques for low leakage circuits based on delay statistics

摘要

A low-leakage circuit design method involves determining a capacity of a power gating transistor using delay statistics, wherein the resulting power gating transistor has sufficient capacity to supply all of the current necessary to meet the demands of the powered design elements while minimizing an amount of chip space required to implement the power gating transistor. The capacity of the power gating transistor is determined by first estimating a capacity necessary to meet the demands of all design elements connected to the transistor. The design elements are then grouped according to input signal arrival time to determine an amount by which the estimated capacity of the gating transistor may be reduced without affecting operation of the design elements. Various grouping schemes are evaluated to determine an optimal grouping. The estimated transistor capacity is reduced according to the optimal grouping, and the power gating transistor is implemented accordingly.