SIMULTANEOUS PIPELINED READ WITH DUAL LEVEL CACHE FOR IMPROVED SYSTEM PERFORMANCE USING FLASH TECHNOLOGY

摘要

A read command protocol (400) and a method of accessing a nonvolatile memory device (100) having an internal cache memory (30-32). A memory device is configured to accept a first and second read command (402, 412), outputting a first requested data (408) from L2 cache (36) through an I/O circuit (40), while simultaneously reading a second requested data (418) from a memory array (10) through a data register (20) into an L1 cache (31). In addition, the memory device may be configured to send or receive a confirmation indicator (406, 416) .