LATENCY OPTIMIZED RESYNCHRONIZATION SOLUTION FOR DDR/DDR2 SDRAM READ PATH
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机译:DDR / DDR2 SDRAM读取路径的延迟优化的重新同步解决方案
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摘要
An apparatus for synchronizing memory data signals is provided. The apparatus comprises a first interface circuit (110) that is configured to generate a differential clock signal in a strobe domain and to convey a data signal to a data bus (110), a second interface circuit (120) in a clock domain that is configured to receive the data signal (170) from the data bus and a synchronization circuit that is configured to adjust the data signal (170) between the strobe domain and the clock domain such that integrity of information encoded by the data signal is preserved. Methods of using the apparatus are also disclosed.
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