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DESIGN OF IP FLOW INFORMATION MANAGEMENT AND EXPORT ARCHITECTURE USING DUAL MEMORIES
DESIGN OF IP FLOW INFORMATION MANAGEMENT AND EXPORT ARCHITECTURE USING DUAL MEMORIES
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机译:基于双记忆的IP流量信息管理和出口架构设计
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摘要
A technique for managing and transmitting IP flow information at high speed by using a dual memory is provided to improve processing performance of a flow device system by solving a problem, which is caused by memory access competition/arbitration for managing, searching, and extracting large flow information, and limit of a data transfer bandwidth of the memory. An accumulating process for accumulating the flow information extracted from received packets to the dual memory(103) is separated from an extracting/transmitting process for extracting/transmitting the flow information accumulated in the dual memory. A memory access speed is maximally used by removing the competition between the processes when a memory bus is used, as a memory for managing the flow information and a memory bus interface(106) are dualized. A flow transmission managing process(105) manages a synchronization signal for enabling both processes to use the dual memory alternatively while separately performing the accumulating and extracting/transmitting process, and synchronizes the signal by using the memory management interface.
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