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BUILT IN SELF TEST AND BUILT IN SELF REPAIR SYSTEM

机译:内置自测和内置自修复系统

摘要

A RAM test and fail repair system is provided to test a RAM with an automatically generated test pattern by adding a BIST(Built In Self Test) and a BISR(Built In Self Repair) circuit in a device and to repair fail bits into normal bits. According to a RAM(Random Access Memory) test and fail repair system, a first operating part(100) includes a RAM(110), an internal register(120) and a fail treatment part(130). The RAM comprises a main RAM and a redundancy cell. The internal register stores a fail address and a good redundancy address. The fail treatment part stores fail address and good redundancy address in the internal register by comparing a test pattern written in the RAM with a test pattern through an internal comparator. A second operating part(200) comprises a RAM address counter(210) generated addresses to access a RAM cell and a comparator(220) comparing the address generated in the RAM address counter with a fail address.
机译:提供了RAM测试和故障修复系统,以通过在设备中添加BIST(内置自检)和BISR(内置自修复)电路来测试具有自动生成的测试模式的RAM,并将故障位修复为正常位。根据RAM(随机存取存储器)测试和故障修复系统,第一操作部分(100)包括RAM(110),内部寄存器(120)和故障处理部分(130)。 RAM包括主RAM和冗余单元。内部寄存器存储故障地址和良好的冗余地址。失败处理部分通过将写入RAM中的测试模式与通过内部比较器的测试模式进行比较,将失败地址和良好冗余地址存储在内部寄存器中。第二操作部分(200)包括:RAM地址计数器(210),其生成的地址用于访问RAM单元;以及比较器(220),其将在RAM地址计数器中生成的地址与失败地址进行比较。

著录项

  • 公开/公告号KR100825068B1

    专利类型

  • 公开/公告日2008-04-24

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR20060071523

  • 发明设计人 천재일;정덕주;이용운;

    申请日2006-07-28

  • 分类号G11C29/00;

  • 国家 KR

  • 入库时间 2022-08-21 19:52:14

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