SEMICONDUCTOR MEMORY DEVICE HAVING WRITE RECOVERY TIME CONTROL CIRCUIT AND METHOD OF CONTROLLING WRITE RECOVERY TIME OF THE SAME

摘要

Wave write recovery time control method of a semiconductor memory device and a semiconductor memory device including the type recovery time control circuit that is controlled in a pipelined manner is disclosed. The semiconductor memory device includes a clock buffer, the command decoder, and the write recovery time control circuit. A clock buffer to generate an internal clock signal based on the external clock signal. The command decoder decodes an external command signal and generates a write command signal. Write recovery time control circuit is the internal clock signal, the write command signal, and on the basis of the write recovery time control signal having a plurality of bits, a plurality of banks pre-charge control signal to the wave pipelined with gating and a plurality of banks pre-gated It generates a charge control signal. Therefore, the write recovery time control circuit a semiconductor memory device with a can to can reduce the number of flip-flops required for the write recovery time control to increase the margin between the input control signals and bank precharge control signal, the power to take up less area when implemented as a semiconductor integrated circuit consumes less.