High-Speed Clock and Data Recovery Circuit using quarter rate clock

摘要

A high-speed clock and data recovery circuit using a quarter frequency clock of data speed, and a method thereof are provided to reduce the size of whole circuit while processing data at a high-speed by recovering a clock and data with the quarter frequency clock of data speed in a situation incapable of generating a high frequency clock. A PLL(Phase Locked Loop) circuit(100) generates a quarter frequency clock of reception data speed by receiving an external clock. A phase interpolation circuit(300) adjusts the phase of the clock output from the PLL circuit to sample the middle part of a received data signal according to a phase control signal received from a clock recovery circuit. A demultiplier circuit(500A,500B) demultiplies the received data signal into halves. The clock recovery circuit(700A,700B) generates the phase control signal for adjusting the phase of the clock by using the demultiplied data signal and the clock output from a phase interpolation circuit. A data determination circuit(900) outputs the middle part of the received data by using the clock adjusted by the clock recovery circuit and the phase interpolation circuit.