MULTIPLE VALUED DYNAMIC RANDOM ACCESS MEMORY CELL AND THEREOF ARRAY USING SINGLE ELECTRON TRANSISTOR

摘要

A multiple value DRAM and a multiple valued DRAM cell array using a single electron transistor are provided to store information above two bits as minimizing power consumption. One end of a first MOS transistor(M1) is connected to a bit line(BL) and the first MOS transistor has a gate connected to a read word line(RWL). One end of a second MOS transistor(M2) is connected to the other end of the first MOS transistor and the other end is connected to a charge charging node(SN), and the second MOS transistor has a gate connected to a write word line(WWL). A third MOS transistor(M3) has one end connected to a common port of the first MOS transistor and the second MOS transistor, and has a gate connected to the charge charging node. A fourth MOS transistor(M4) has one end connected to the charge charging node and has a gate receiving a refresh signal(SSG). A fifth MOS transistor(M5) has one end connected to the charge charging node and has a gate receiving the refresh signal. A SET(Single Electron Transistor) has one end connected to the other end of the fifth MOS transistor and the other end connected to a second power supply port(Vss) and has a gate connected to the charge charging node. A storage capacitor(Cs) has one end connected to the charge charging node and the other end connected to the second power supply port.