2-Transistor NOR-type non-volatile memory cell array and Method for processing 2-Transistor NOR-type non-volatile memory data.

摘要

2T having the select transistor and the floating gate or the charge accumulation charge accumulation storage transistor having an insulator a NOR cell array, and 2T NOR flash memory cells, a data processing method that is used to read or erase the stored data, or to store data in the 2T NOR cell array is disclosed. The 2T NOR cell array is provided with a selection transistor and the storage transistor. The selection transistor is connected to a terminal is applied to the bit line selection signal to the gate terminal. The storage transistor is a terminal connected to the other terminal of the selection transistor and the other terminal connected to a common source line, and the control voltage applied to the gate. Is applied to the select transistor and the bulk (Bulk) area, back bias (Back Bias) is the program voltage of the storage transistor, and a floating gate or the charge accumulation insulator between the gate and the bulk region of the storage transistor.