Electrically erasable programmable-read only memory cell for use in latch circuit, has floating gate with recess, in which layer thickness of floating gate is reduced, and intermediate-dielectric enclosing floating gate at edge cover

摘要

The cell has a source (S) and a drain (D), which are arranged on both sides of a canal area (KG) in a semiconductor substrate (SU). A gate stack is arranged above the canal area and comprises a layer assembly from a gate-dielectric (GD), a floating gate (FG), an intermediate-dielectric (ZD) and a control gate (CG). The floating gate exhibits a recess, in which the layer thickness of the floating gate is reduced compared to the rest of the gate surface. The intermediate-dielectric encloses the floating gate at edge cover.