首页> 外国专利> Interface circuit has calibration circuit, sampling signal, data signal delay circuit, and minimum delay time that is in calibration circuit, which is displaced between data signal and sampling signal

Interface circuit has calibration circuit, sampling signal, data signal delay circuit, and minimum delay time that is in calibration circuit, which is displaced between data signal and sampling signal

机译:接口电路具有校准电路,采样信号,数据信号延迟电路和校准电路中的最小延迟时间,该延迟时间在数据信号和采样信号之间移动

摘要

The interface circuit (10) has a calibration circuit for automatic detecting of a valid data window of a data signal and adjusting of an optimal delay of a sampling signal. A data signal delay circuit for delaying the data signal at a delay time, which fulfill a certain equation. The minimum delay time is in the calibration circuit, which is displaced between the data signal and the sampling signal and is the setup-time of the data signal.
机译:接口电路(10)具有校准电路,用于自动检测数据信号的有效数据窗口并调整采样信号的最佳延迟。一种数据信号延迟电路,用于在延迟时间延迟数据信号,该信号满足特定方程式。最小延迟时间在校准电路中,该时间在数据信号和采样信号之间移动,并且是数据信号的建立时间。

著录项

  • 公开/公告号DE102007039615A1

    专利类型

  • 公开/公告日2008-02-28

    原文格式PDF

  • 申请/专利权人 NEC ELECTRONICS CORP.;

    申请/专利号DE20071039615

  • 发明设计人 IIZUKA YOICHI;

    申请日2007-08-22

  • 分类号H04L7/04;G11C7/22;

  • 国家 DE

  • 入库时间 2022-08-21 19:49:14

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