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Semiconductor memory unit has multiple fin semiconductors, and gate electrode is provided in recess, which is located between fin semiconductors and are adjacent to each other and another gate electrode

机译:半导体存储单元具有多个鳍状半导体,并且栅电极设置在凹部中,该凹部位于鳍状半导体之间并且彼此相邻,并且另一个栅电极

摘要

The semiconductor memory unit has multiple fin semiconductors. A gate electrode, which is provided in a recess, which is located between the fin semiconductors and are adjacent to each other and another gate electrode, which are provided in another recess adjacent to the former recess and are located between the fin semiconductors, and are adjacent to each other. The bit lines are connected with the drain layers, and extend in the former direction.
机译:半导体存储单元具有多个鳍状半导体。设置在彼此相邻的位于鳍状半导体之间的凹部中的栅电极和设置在鳍状半导体之间且与前一个凹部相邻的另一个凹部中的另一栅电极,所述栅电极位于鳍状半导体之间。彼此相邻。位线与漏极层连接,并沿前一方向延伸。

著录项

  • 公开/公告号DE102008011696A1

    专利类型

  • 公开/公告日2008-09-04

    原文格式PDF

  • 申请/专利权人 KABUSHIKI KAISHA TOSHIBA;

    申请/专利号DE20081011696

  • 发明设计人 OHSAWA TAKASHI;

    申请日2008-02-28

  • 分类号H01L27/105;G11C11/407;

  • 国家 DE

  • 入库时间 2022-08-21 19:49:08

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