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LAYOUT DESIGN PROGRAM, RECORDING MEDIUM HAVING THE PROGRAM RECORDED THEREIN, LAYOUT DESIGN SYSTEM, AND LAYOUT DESIGN METHOD

机译:布局设计程序,具有录制在其中的程序的记录介质,布局设计系统和布局设计方法

摘要

PPROBLEM TO BE SOLVED: To achieve regular wiring density and edge length after wiring is completed. PSOLUTION: When wiring layout is determined, maximum values of the wiring density and edge length of wiring in each of partial regions are limited. After the wiring layout, minimum values of the wiring density and edge length of each partial region are limited by inserting dummy wiring in one of the partial regions having a small wiring density. Consequently, the wiring density and edge length of each partial region can be suppressed within constant ranges and irregularities on the surface of a substrate after polished can be reduced. PCOPYRIGHT: (C)2009,JPO&INPIT
机译:

要解决的问题:完成布线后要达到规则的布线密度和边长​​。

解决方案:确定布线布局时,每个局部区域中的布线密度和布线边缘长度的最大值受到限制。在布线布局之后,通过在具有小布线密度的部分区域之一中插入虚设布线来限制每个部分区域的布线密度和边缘长度的最小值。因此,可以将每个局部区域的布线密度和边缘长度抑制在恒定范围内,并且可以减少抛光后的基板表面上的不规则性。

版权:(C)2009,日本特许厅&INPIT

著录项

  • 公开/公告号JP2009111244A

    专利类型

  • 公开/公告日2009-05-21

    原文格式PDF

  • 申请/专利权人 FUJITSU LTD;

    申请/专利号JP20070283393

  • 发明设计人 FUKUDA DAISUKE;

    申请日2007-10-31

  • 分类号H01L21/82;H01L21/822;H01L27/04;H01L21/3205;H01L23/52;G06F17/50;

  • 国家 JP

  • 入库时间 2022-08-21 19:43:36

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