EQUIVALENCE VERIFYING METHOD, EQUIVALENCE VERIFICATION PROGRAM AND METHOD FOR GENERATING EQUIVALENCE VERIFICATION PROGRAM

摘要

PPROBLEM TO BE SOLVED: To provide a verifying method for using a test bench for a basic circuit model in verifying the equivalence of a new circuit to be developed for the basic circuit model. PSOLUTION: In order to verify the equivalence of a model by using an example model with a circuit described in a prescribed language and a test vector generation model for the example model, the following processing are performed: writing an output from the test vector generation model for the example model in an input FIFO group for each signal of the example model at the same timing as that of the example model while inputting and outputting signals between the example model and the test vector generation model for the example model;and reading data from the input FIFO group at the same operating timing as that of the verification target model and outputting the data to the verification target model. Each signal name of the output of the example model corresponding to the output of the verification target model is written in an output FIFO pair group, and matching is determined with respect to an output pair for each written signal name. PCOPYRIGHT: (C)2010,JPO&INPIT