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High speed hybrid structure counter having synchronous timing and asynchronous counter cells
High speed hybrid structure counter having synchronous timing and asynchronous counter cells
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机译:具有同步定时和异步计数器单元的高速混合结构计数器
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摘要
A multi-bit counter is provided. The multi-bit counter includes a plurality of asynchronous base counter cells coupled in series, the asynchronous base counter cells having a plurality of input terminals. The multi-bit counter also includes at least one logic gate coupled to at least one of the input terminals of at least one of the plurality of asynchronous base counter cells, a reload signal being input into the asynchronous base counter cells, a clock signal being input into the asynchronous base counter cells, and an input voltage being input into the asynchronous base counter cells, wherein the multi-bit counter is synchronous with the clock signal.
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