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ON-CHIP CIRCUIT FOR TRANSITION DELAY FAULT TEST PATTERN GENERATION WITH LAUNCH OFF SHIFT
ON-CHIP CIRCUIT FOR TRANSITION DELAY FAULT TEST PATTERN GENERATION WITH LAUNCH OFF SHIFT
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机译:带有转换启动的过渡延时故障测试图生成的芯片上电路
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摘要
A clock pulse controller includes a test clock pulse input for receiving test clock pulses. A scan enable input receives a scan enable signal having a first state and a second state. A trigger pulse input receives a trigger pulse. A clock pulse output generates a launch clock pulse and a capture clock pulse from the test clock pulses immediately after receiving a predetermined number of the test clock pulses immediately following the trigger pulse. A delayed scan enable output generates a delayed scan enable signal that transitions from the first state to the second state between a leading edge of the launch clock pulse and a leading edge of the capture clock pulse.
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