Stall-Free Pipelined Cache for Statically Scheduled and Dispatched Execution

摘要

This invention provides flexible load latency to pipeline cache misses. A memory controller selects the output of one of a set of cascades inserted execute stages. This selection may be controlled by a latency field in a load instruction or by a latency specification of a prior instruction. This invention is useful in the great majority of cases where the code can tolerate incremental increases in load latency for a reduction in cache miss penalty.