PLL circuit having reduced pull-in time

摘要

The PLL circuit of the present invention includes a voltage-controlled oscillator, a loop filter, and a charge pump which controls a voltage of the loop filter while the voltage-controlled oscillator is not oscillating. Therefore, it is possible, even while the voltage-controlled oscillator is not oscillating, to control a voltage for the charge pump so that it is equal to a voltage when the voltage-controlled oscillator is oscillating at a predetermined frequency. Accordingly, by the loop filter outputting a voltage signal to the voltage-controlled oscillator when the PLL circuit is turned on, the pull-in time can be shortened.