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Analytic structure for failure analysis of semiconductor device having a multi-stacked interconnection structure
Analytic structure for failure analysis of semiconductor device having a multi-stacked interconnection structure
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机译:具有多层堆叠互连结构的半导体器件的失效分析的解析结构
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摘要
In an analytic structure for failure analysis of a semiconductor device, a plurality of analytic regions are arranged in regions of a semiconductor substrate. A plurality of semiconductor transistors having an array structure are arranged in each of the analytic regions. A plurality of interconnection structures connect the semiconductor transistors, each comprising multiple layered metal patterns and multiple layered plugs interposed between the multiple layered metal patterns. A first number of layers of the multiple layered metal patterns and multiple layered plugs is different in one of the analytic regions than a second number of layers of the multiple layered metal patterns and multiple layered plugs in another one of the analytic regions.
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