Processes providing high and low threshold p-type and n-type transistors

摘要

Methods of fabricating negative-channel metal-oxide semiconductor (NMOS) devices and positive-channel metal-oxide semiconductor (PMOS) devices having complementary threshold voltages are described. Elements of lower-threshold voltage NMOS devices are formed at first locations on a substrate. Elements of higher-threshold voltage PMOS devices are formed at second locations on the substrate. Elements of higher-threshold voltage NMOS devices and elements of lower-threshold PMOS devices are formed by adding a same amount of p-type dopant at selected locations chosen from the first and second locations.