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Method and computer program for static timing analysis with delay de-rating and clock conservatism reduction
Method and computer program for static timing analysis with delay de-rating and clock conservatism reduction
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机译:具有延迟降额和时钟保守性降低的静态时序分析的方法和计算机程序
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摘要
A method and computer program for static timing analysis includes receiving as input minimum and maximum stage delays for two corners of an integrated circuit design. A path slack for a setup timing check is calculated from the minimum and maximum stage delays as a function of net clock cycle interval T_clk, launch path delay T_LP, capture path delay T_CP, data path delay T_DP, and a first delay de-rating factor Y1. A path slack for a hold timing check is calculated from the minimum and maximum stage delays as a function of the launch path delay T_LP, the capture path delay T_CP, the data path delay T_DP, and a second delay de-rating factor Y2. The path slack calculated for the setup timing check and for the hold timing check is generated as output.
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