Synchronous SRAM capable of faster read-modify-write operation

摘要

An improved synchronous SRAM capable of faster read-modify-write cycle time using separate input and output terminals. It describes the circuitry for performing a RMW operation in a memory module at high frequency in a nanometer technology. A byte write enable bus is incorporated into the device so as to provide the flexibility of modification and correction at selective columns, keeping rest of the columns unaltered. The termination of read operation and the triggering of write operation is done by the activation of same signal. Also described is the provision for tuning the circuitry for triggering write operation depending on the time taken by the controller to modify and revise the read-out data.