INTRA/INTER CHIP COMMUNICATION CIRCUIT, COMMUNICATION METHOD, AND THREE-DIMENSIONAL LSI DEVICE

摘要

A communication circuit and method capable of fixing latency. Clocks (300, 200) through clock distribution circuits (11, 10) from clock generating circuits (2, 1) are distributed to transmitting/receiving circuits (6, 5). In the transmitting/receiving circuit (5), a signal (301) transmitted from the transmitting/receiving circuit (6) allows an over-sampling circuit/phase generating circuit (123) to perform time adjustment equivalent to a high frequency component (varying at a frequency with a high clock time difference) of the clock time difference between the transmitting circuit and the receiving circuit, is transmitted to a variable latency buffer (122), detects what cycle a low frequency component (varying at a frequency with a low clock time difference) of the clock time difference detected by a low frequency phase difference detecting circuit (121) is equivalent to, converts the difference between a predetermined time and the low frequency component of the clock time difference into the number of cycles, allows the variable latency buffer (122) to perform the time adjustment, and is transmitted to a flip-flop (101).