Iterative decoding of low-density parity-check (LDPC) codes

摘要

An LDPC decoder has been designed that has reduced power requirements. After an initial parity check, the decoder holds in a register a flip indicator array with 0-values for those bits of the received codeword that satisfy a parity check, and 1-values for those bits that fail the parity check. In subsequent iterations, updates are performed on these bits rather than directly on the data bits. As a consequence, power requirements will be reduced.