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CHIP-PACKAGE SIMULATION

机译:芯片包装模拟

摘要

A computer implemented method, data processing system, and computer usable program code are provided for reducing a chip package model. Responsive to receiving the chip package model, an inductance and a resistance of the chip package model is measured. The inductance and the resistance are measured using only a set of external nodes of the chip package model. A reduced node resistor model and a reduced node inductor model are created using the inductance and the resistance of the chip package model. A combined reduced node resistor-inductor chip package model is formed by combining the reduced node resistor model and reduced node inductor model.
机译:提供了一种计算机实现的方法,数据处理系统和计算机可用程序代码,用于减少芯片封装模型。响应于接收芯片封装模型,测量芯片封装模型的电感和电阻。仅使用芯片封装模型的一组外部节点测量电感和电阻。使用芯片封装模型的电感和电阻来创建精简节点电阻器模型和精简节点电感器模型。通过组合简化节点电阻器模型和简化节点电感器模型来形成组合的简化节点电阻器-电感器芯片封装模型。

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