INTERNAL COMMAND SIGNAL GENERATION CIRCUIT AND A GENERATING METHOD THEREOF, CAPABLE OF REDUCING A CHIP SIZE BY OPTIMIZING A SIZE OF A CIRCUIT SELECTING THE SIGNAL CORRESPONDING TO A WRITE LATENCY

摘要

PURPOSE: An internal command signal generation circuit and a generating method thereof are provided to minimize the power consumption for generating a write command signal corresponding to the write latency by controlling a shifting operation selectively according to the write latency.;CONSTITUTION: A clock signal controller controls the activation of a second clock signal corresponding to a first clock signal in response to the write latency. A first shifting unit(230) shifts an input signal in response to the first clock signal. A second shifting unit(250) shifts a source write command signal in response to a second clock signal activated in a larger write latency than the preset latency. An internal command signal multiplexer(270) selectively outputs the source write command signal in response to the write latency and the output signal of the first shifting unit as the internal command signal.;COPYRIGHT KIPO 2010