SAMPLE AND HOLD CIRCUIT, AND METHOD FOR REDUCING TIMING MISMATCH IN SAMPLE AND HOLD CIRCUIT

摘要

The present invention relates to a high-speed sample / hold circuit comprising a plurality of sample / hold subcircuits (sample and hold subcircuits) connected in parallel between the input and the output. Circuit further comprises a plurality of sample / hold circuits connected to the sub-circuit and the correction (calibration circuit). Correction circuit to reduce the number of samples / by operable to change the hold signal for one or more of the hold subcircuits, timing between a plurality of sample / hold subcircuits and the associated distortion mismatch (timing mismatch) can. The invention also includes a method for reducing timing mismatch in high speed parallel-connected sample / hold circuit. The method comprises detecting timing mismatch associated with the plurality of sample / hold subcircuits, and includes changing one or more of the hold signal for the subcircuits. In one exemplary method, the sample / hold circuit converts the output data into digital data, performs a FFT (Fast Fourier Transform) about it, by analyzing the energy spectrum can be obtained as a result, it detects the timing mismatch . ; Sample / hold circuit, a timing mismatch, the calibration circuit, the FFT