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S during eldi gate driver and the driving method for driving

机译:Eldi门驱动器中的S及驱动方法

摘要

PURPOSE: A gate driver using an SCLD(Shared Column-Line Driving) method and a driving method thereof are provided to simplify a total structure and stabilize a driving operation by reducing the number of shift registers within the gate driver. CONSTITUTION: A gate driver using an SCLD method includes a shift register, an output controller, a level shifter, and an output buffer. The shift register(210) is used for receiving and outputting the first and the second Vsync signals, a clock signal, and a carry signal. The output controller(220) is used for receiving an odd OE signal and an even OE signal and outputting the carry signal of the shift register. The level shifter(230) is used for converting the carry signal of the output controller to a voltage level according to the clock signal. The output buffer(240) is used for receiving the converted voltage of the level shifter and outputting the converted voltage to an odd and an even gate line according to the odd OE signal and the even OE signal.
机译:目的:提供一种使用SCLD(共享列线驱动)方法的栅极驱动器及其驱动方法,以通过减少栅极驱动器内的移位寄存器的数量来简化总体结构并稳定驱动操作。构成:采用SCLD方法的栅极驱动器包括移位寄存器,输出控制器,电平移位器和输出缓冲器。移位寄存器(210)用于接收和输出第一和第二Vsync信号,时钟信号和进位信号。输出控制器(220)用于接收奇数OE信号和偶数OE信号并输出​​移位寄存器的进位信号。电平转换器(230)用于根据时钟信号将输出控制器的进位信号转换为电压电平。输出缓冲器(240)用于接收电平转换器的转换电压,并根据奇数OE信号和偶数OE信号将转换后的电压输出到奇数和偶数栅极线。

著录项

  • 公开/公告号KR100908203B1

    专利类型

  • 公开/公告日2009-07-20

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR20020088536

  • 发明设计人 권순영;백종상;

    申请日2002-12-31

  • 分类号G09G3/36;

  • 国家 KR

  • 入库时间 2022-08-21 19:11:49

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