HIGH-INTEGRITY DIGITAL PROCESSING ARCHITECTURE WITH MULTIPLE SUPERVISED RESOURCES

摘要

The present invention relates to computers whose undetected errors must have a very low rate of occurrence (10 -9 per unit of time). This concerns in particular the onboard computers on aircraft running critical applications such as autopilot, flight management, fuel management or anti-collision terrain. Two or more calculation channels are planned and the exchanges are authorized either at the production or at the consumption of the data by each way. It is also possible to provide a predefined authorization cycle. The transfer authorization of the data is given according to a binary comparison logic in the case of two channels. In the case of more than two channels, the authorization can be given either by a logic of comparison binary or by a majority logic according to which one privileges the integrity or the availability of the system of computation.