HIGH-INTEGRITY COMPUTATION ARCHITECTURE WITH MULTIPLE SUPERVISED RESOURCES

摘要

The present invention relates to computers, the undetected errors of which have a very low rate of occurrence (approximately 10⁻⁹ per time unit). This relates in particular to the embedded computers on aircraft that run critical applications such as the automatic pilot, flight management, fuel management or terrain collision prevention. Two or more computation lanes or sections are provided and the exchanges are authorized either on the production or on the consumption of the data by each of the lanes. It is also possible to provide a predefined authorization cycle. The authorization to transfer the datum is given according to a binary comparison logic in the case of two lanes. In the case of more than two lanes, the authorization can be given either by a binary comparison logic or by a majority logic depending on whether the integrity or the availability of the computation system is prioritized.