首页> 外国专利> DYNAMIC SUBSTRATE BIAS SYSTEM SUPPRESSING NEGATIVE BIAS TEMPERATURE INSTABILITY AND METHOD FOR THE SAME

DYNAMIC SUBSTRATE BIAS SYSTEM SUPPRESSING NEGATIVE BIAS TEMPERATURE INSTABILITY AND METHOD FOR THE SAME

机译:抑制负偏置温度不稳定性的动态基底偏置系统及其方法

摘要

PPROBLEM TO BE SOLVED: To improve performance of a circuit by a system and a method for suppressing negative bias temperature instability in a P-channel MOS transistor. PSOLUTION: The system for suppressing the negative bias temperature instability in the P-channel CMOS transistor and a method for the system are disclosed. The system includes the P-channel CMOS transistor and a voltage control circuit. A source pole for the P-channel CMOS transistor in the system is connected to a power supply, and the voltage control circuit is mounted so as to output a first potential and a second potential. The first potential differs from the second voltage, the first potential is lower than a power supply voltage and the second potential is higher than or equal to the power supply voltage. When the P-channel MOS transistor in the system is turned on, the first potential is applied to a substrate for the P-channel MOS transistor. When the P-channel MOS transistor is turned off, the second potential is applied to the substrate for the P-channel MOS transistor. PCOPYRIGHT: (C)2010,JPO&INPIT
机译:

要解决的问题:通过用于抑制P沟道MOS晶体管中的负偏置温度不稳定性的系统和方法来改善电路的性能。

解决方案:公开了一种用于抑制P沟道CMOS晶体管中的负偏置温度不稳定性的系统和该系统的方法。该系统包括P沟道CMOS晶体管和电压控制电路。系统中用于P沟道CMOS晶体管的源极连接到电源,并且电压控制电路被安装以便输出第一电势和第二电势。第一电势不同于第二电压,第一电势低于电源电压,并且第二电势高于或等于电源电压。当系统中的P沟道MOS晶体管导通时,第一电势被施加到P沟道MOS晶体管的衬底。当P沟道MOS晶体管截止时,第二电势被施加到用于P沟道MOS晶体管的基板。

版权:(C)2010,日本特许厅&INPIT

著录项

  • 公开/公告号JP2010109969A

    专利类型

  • 公开/公告日2010-05-13

    原文格式PDF

  • 申请/专利权人 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD;

    申请/专利号JP20090209804

  • 发明设计人 WU WEI-HAO;OATES ANTHONY;

    申请日2009-09-10

  • 分类号H03K19/094;H03K19/0948;H01L21/822;H01L27/04;

  • 国家 JP

  • 入库时间 2022-08-21 19:06:00

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