首页> 外国专利> NOTCH-FREE ETCHING OF HIGH ASPECT RATIO SOI STRUCTURES USING ALTERNATING DEPOSITION AND ETCHING AND USING PULSED PLASMA

NOTCH-FREE ETCHING OF HIGH ASPECT RATIO SOI STRUCTURES USING ALTERNATING DEPOSITION AND ETCHING AND USING PULSED PLASMA

机译:使用交替沉积和蚀刻以及使用脉冲等离子体对高纵横比SOI结构进行无缺口蚀刻

摘要

PROBLEM TO BE SOLVED: To provide a method of preventing notching during cyclical etching and deposition on a substrate via an inductively coupled plasma source.;SOLUTION: In accordance with the method, the inductively coupled plasma source generates pulses to prevent charge from being accumulated on the substrate. The off state of the inductively coupled plasma source is long enough to permit a charge outflow, but it is not so long as a low duty cycle causes the reduction of an etching rate. The pulse generation may be controlled such that pulses are generated only when the substrate is etched to expose an insulating layer. A bias voltage may also be applied to the insulating layer. The bias voltage may be pulsed in phase or out of phase with pulse generation in the inductively coupled plasma source.;COPYRIGHT: (C)2010,JPO&INPIT
机译:解决的问题:提供一种防止在周期性蚀刻和经由电感耦合等离子体源沉积在基板上的过程中产生缺口的方法;解决方案:根据该方法,电感耦合等离子体源产生脉冲以防止电荷在其上累积基板。电感耦合等离子体源的截止状态足够长以允许电荷流出,但是只要低占空比导致蚀刻速率降低就可以。可以控制脉冲的产生,使得仅当蚀刻衬底以暴露绝缘层时才产生脉冲。偏置电压也可以施加到绝缘层。偏置电压可以与感应耦合等离子体源中的脉冲产生同相或异相脉冲。;版权所有:(C)2010,JPO&INPIT

著录项

  • 公开/公告号JP2010206219A

    专利类型

  • 公开/公告日2010-09-16

    原文格式PDF

  • 申请/专利权人 UNAXIS USA INC;

    申请/专利号JP20100130064

  • 申请日2010-06-07

  • 分类号H01L21/3065;H05H1/24;H05H1/46;

  • 国家 JP

  • 入库时间 2022-08-21 19:05:34

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