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Phase-locked loop circuit having deadlock prevention circuit and deadlock prevention method thereof

机译:具有防死锁电路的锁相环电路及其防死锁方法

摘要

A phase locked loop (PLL) circuit having a deadlock protection circuit and a deadlock protection method of the PLL circuit are provided. The PLL circuit includes: a phase frequency detector, which receives an input clock signal and a divided clock signal and compares the phase and frequency of the input clock signal with the phase and frequency of the divided clock signal; a charge pump, which receives an output signal of the phase frequency detector; a voltage-controlled oscillator, which oscillates in response to an output voltage of the charge pump; a main divider, which divides the frequency of an first output clock signal of the voltage-controlled oscillator and outputs the divided clock signal as the division resu and a deadlock protection circuit, which is electrically coupled to an output port of the voltage-controlled oscillator and an input port of the main divider, and divides the frequency of the first output clock signal of the voltage-controlled oscillator and then provides the division result to the main divider if the frequency of the first output clock signal of the voltage-controlled oscillator is above a threshold frequency.
机译:提供一种具有死锁保护电路的锁相环(PLL)电路和该PLL电路的死锁保护方法。 PLL电路包括:相位频率检测器,其接收输入时钟信号和分频时钟信号,并将输入时钟信号的相位和频率与分频时钟信号的相位和频率进行比较;以及电荷泵,其接收所述相位频率检测器的输出信号;压控振荡器,其响应于电荷泵的输出电压而振荡;主分频器,对压控振荡器的第一输出时钟信号的频率进行分频,并输出分频后的时钟信号作为分频结果;死锁保护电路,其电性耦接至压控振荡器的输出端口与主分频器的输入端口,并对压控振荡器的第一输出时钟信号的频率进行分频,然后进行分频。如果压控振荡器的第一输出时钟信号的频率高于阈值频率,则向主分频器求和。

著录项

  • 公开/公告号JP4520937B2

    专利类型

  • 公开/公告日2010-08-11

    原文格式PDF

  • 申请/专利权人 三星電子株式会社;

    申请/专利号JP20050358194

  • 发明设计人 呉 政勳;

    申请日2005-12-12

  • 分类号H03L7/095;H03L7/199;

  • 国家 JP

  • 入库时间 2022-08-21 19:02:24

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