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METHOD OF DESIGNING SUBSTRATE INCLUDING PROGRAMMABLE LOGIC CIRCUIT SUCH AS FPGA

机译:FPGA等包含可编程逻辑电路的基板设计方法

摘要

PROBLEM TO BE SOLVED: To provide a layout having the shortest wiring distance between an FPGA (Field Programmable Gate Array) pin and a peripheral circuit pin corresponding thereto.;SOLUTION: This substrate design method includes: a step for performing the circuit design of a pin-unassigned FPGA 3 and a memory 5 as a pin-assigned peripheral circuit; a step for laying out the FPGA 3 and the memory 5 on a substrate according to the circuit design; and a step for assigning the FPGA pin 40 among the FPGA pins 34, 35, 40 and 41 to the pin connected to the address pin 51 of the corresponding memory 5 with the shortest wiring distance.;COPYRIGHT: (C)2010,JPO&INPIT
机译:解决的问题:提供一种布局,使FPGA(现场可编程门阵列)引脚和与其对应的外围电路引脚之间的布线距离最短;解决方案:该基板设计方法包括:执行电路设计的步骤未分配引脚的FPGA 3和作为引脚分配的外围电路的存储器5;根据电路设计将FPGA 3和存储器5布置在基板上的步骤; ;以及将FPGA引脚34、35、40和41中的FPGA引脚40分配给连接到具有最短布线距离的对应存储器5的地址引脚51的引脚的步骤。版权所有:(C)2010,JPO&INPIT

著录项

  • 公开/公告号JP2010079357A

    专利类型

  • 公开/公告日2010-04-08

    原文格式PDF

  • 申请/专利权人 KOYO ELECTRONICS IND CO LTD;

    申请/专利号JP20080243794

  • 发明设计人 YOKOO MASAHIKO;

    申请日2008-09-24

  • 分类号G06F17/50;H01L21/82;H01L21/822;H01L27/04;

  • 国家 JP

  • 入库时间 2022-08-21 19:01:22

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