Diode array architecture for handling nanoscale resistive memory array

摘要

This memory constitution to be connected, the 1st conductor (BL) with, the 2nd conductor (WL) with, the 2nd conductor (WL) the resistant memory cell which is connected (130) with, resistant memory cell (130) and the 1st conductor (BL) at the same time, resistant memory cell (130) from the 1st conductor (BL) to the 1st diode which orientation is done (134) with, the 1st diode (134) with in parallel, resistant memory cell (130) and the 1st conductor (BL) to be connected by forward direction, at the same time, resistant memory cell (130) from the 1st conductor (BL) to the 2nd diode which orientation is done (132) with it includes in opposite direction. The 1st and 2nd diode (134 and 132) it possesses the threshold voltage which differs.