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Trace Containment Detection of Combinational Designs via Constraint-Based Uncorrelated Equivalence Checking

机译:通过基于约束的不相关等效检查来检测组合设计的痕量遏制

摘要

Methods and systems are provided for producing more efficient digital circuitry designs by identifying trace-containment for a sequential circuitry design netlist through the use of constraint-based uncorrelated equivalence checking. A set of candidate input netlist sets n1 and n2 is first uncorrelated and then submitted for equivalence checking. Mismatches discovered during the equivalence checking are avoided by imposing constraint to the input set until discovering an equivalency relationship between the input sets n1 and n2.
机译:提供了用于通过使用基于约束的不相关等效检查来识别顺序电路设计网表的迹线包含,从而产生更有效的数字电路设计的方法和系统。一组候选输入网表集n 1 和n 2 首先是不相关的,然后提交进行等效性检查。通过对输入集施加约束,直到发现输入集n 1 和n 2之间的等价关系,可以避免在等价性检查期间发现的不匹配。

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