LOGIC TESTER AND METHOD FOR SIMULTANEOUSLY MEASURING DELAY PERIODS OF MULTIPLE TESTED DEVICES

摘要

The invention provides a logic tester. In one embodiment, the logic tester is coupled to a plurality of tested devices, and includes a function generator and a pattern comparator. The function generator generates an initial code sequence as an input signal of the tested devices to fix output signals of the tested devices to a first value, and then generates a functional code sequence as the input signal of the tested devices to trigger the output signals of the tested devices to change from the first value to a second value. The pattern comparator converts the output signals of the tested devices to a plurality of bitstreams after the functional code sequence is generated, calculates numbers of bits corresponding to the first value in the bitstreams, estimates delay periods of the tested devices according to the numbers of bits, and outputs the delay periods of the tested devices.