首页> 外国专利> CLOCK TIMING CALIBRATION CIRCUIT AND CLOCK TIMING CALIBRATION METHOD FOR CALIBRATING PHASE DIFFERENCE BETWEEN DIFFERENT CLOCK SIGNALS AND RELATED ANALOG-TO-DIGITAL CONVERSION SYSTEM USING THE SAME

CLOCK TIMING CALIBRATION CIRCUIT AND CLOCK TIMING CALIBRATION METHOD FOR CALIBRATING PHASE DIFFERENCE BETWEEN DIFFERENT CLOCK SIGNALS AND RELATED ANALOG-TO-DIGITAL CONVERSION SYSTEM USING THE SAME

机译:用于校准不同时钟信号与相关模拟到数字转换系统之间的相位差的时钟时序校准电路和时钟时序校准方法

摘要

A clock timing calibration circuit includes a clock timing adjusting unit and a calibration control unit. The clock timing adjusting unit is for receiving an incoming reference clock signal and selectively adjusting the received reference clock signal to generate a first clock signal according to a calibration control signal. The incoming reference clock has a predetermined phase and a predetermined frequency, The calibration control unit is for checking if the phase difference between the first clock signal and a second clock signal satisfies a predetermined criterion, and for adjusting the calibration control signal when the phase difference between the first clock signal and the second clock signal does not satisfy the predetermined criterion. The predetermined criterion is to check if the phase difference falls within a specific range associated with a clock period of one of the first clock signal and the second clock signal.
机译:时钟时序校准电路包括时钟时序调整单元和校准控制单元。时钟时序调整单元用于接收输入参考时钟信号,并根据校准控制信号选择性地调整接收到的参考时钟信号以产生第一时钟信号。输入的参考时钟具有预定的相位和预定的频率。校准控制单元用于检查第一时钟信号和第二时钟信号之间的相位差是否满足预定标准,并且当相位差时调整校准控制信号。第一时钟信号和第二时钟信号之间的“α”不满足预定标准。预定准则是检查相位差是否落在与第一时钟信号和第二时钟信号之一的时钟周期相关联的特定范围内。

著录项

  • 公开/公告号US2010066422A1

    专利类型

  • 公开/公告日2010-03-18

    原文格式PDF

  • 申请/专利权人 JEN-CHE TSAI;

    申请/专利号US20090479877

  • 发明设计人 JEN-CHE TSAI;

    申请日2009-06-08

  • 分类号H03L7;

  • 国家 US

  • 入库时间 2022-08-21 18:55:14

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