TWO-STEP SUB-RANGING ANALOG-TO-DIGITAL CONVERTER AND METHOD FOR PERFORMING TWO-STEP SUB-RANGING IN AN ANALOG-TO-DIGITAL CONVERTER

摘要

A two-step ADC is provided that achieves significant improvements in the settling time window available for CDAC conversion, FADC sub-ranging and FADC conversion without increasing the amount of chip area or power that are consumed by the ADC. The ADC uses interleaved sampler/buffer circuits to sample the incoming analog signal on different phases of the clock signal. MUXes provide the samples obtained by the sampler/buffer circuits to the CADC and FADC circuits in ping pong fashion in such a way that the CADC and FADC circuits are converting during every clock period. In addition, these improvements are achieved without increasing the number of potential sources of bit decision mismatches in the two-step sub-ranging ADC.