The present invention provides a sub-ranging analog-to-digital (A / D) converter 10 having improved speed and power consumption characteristics with respect to known sub-ranging converters. The sub-raising A / D converter uses information related to the bit values determined in one stage 12 to define the operating range for the subsequent stage 14. In one embodiment, the subsequent stage uses three input comparators 48 to determine the bit value. Two of the inputs are used to receive signals representing the upper and lower limits of the operating range determined by the preceding stage and the other input is used to receive the analog signal 18. The three input comparator is operative to generate an output signal representing the relationship of the analog signal to a threshold level within the limited range of operation determined by the preceding stage.
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